1. Field of the Invention
This invention relates to serial communication circuits and more particularly to power management techniques employed within asynchronous receiver and transmitter circuits.
2. Description of the Relevant Art
A universal asynchronous receiver and transmitter, commonly abbreviated as a UART, is a prevalently employed communications element within computer systems that allows serial data transmission and reception. A major task of a UART is parallel-to-serial and serial-to-parallel conversion. Briefly speaking, a typical UART includes a pair of shift registers with associated FIFO buffers and control logic. Data to be serially transmitted is loaded into an output shift register, which is clocked at a predetermined bit rate. Start and stop bits are typically inserted that surround each data word during the serial data transmission. Serial data received by the UART is fed into an input shift register, and is clocked at the mid-point of each bit cell. The mid-point of each bit cell is determined by measuring the time relative to the start bit. When a complete word of data is received, the word is transferred into the FIFO buffer in parallel format. When the FIFO buffer is filled to a predetermined capacity, a microprocessor of the computer system is typically interrupted and the data is unloaded from the FIFO buffer.
A typical UART further includes a variety of control and status registers that set and indicate various operating parameters, including the number of data bits, the number of stop bits, the type of parity, the clock divisor, and the status of the internal FIFO buffers. In addition to the basic serial input and output functions, most UART circuits also include connections for modem control handshake signals for RS-232 operation. Details regarding specific UART circuits may be found in a host of publications of the known prior art.
One problem associated with typical UART circuits is that the serial input and output ports usually remain idle for a significant portion of time. During the idle condition of a UART, the receiver state machine which controls the receipt of serial input data is clocked by the internal baud rate generator even though data is not actually being received. The receiver state machine is continuously clocked since the times at which data will be received are usually not known ahead of time. In addition to the receiver state machine, the baud rate generator may also clock other portions of the UART circuit during the idle condition. As a result, power is wasted when the UART is idle since the baud rate signal is unnecessarily being generated and provided to various internal portions of the UART. This is a particular problem when UART circuits are employed within battery-powered portable computer systems.